1. Field of the Invention
The present invention generally relates to packaging of electronic systems with microprocessors including central processing units (CPUs), and in particular to electronic systems integrating multiple microprocessors and auxiliary devices.
2. Relevant Background
Microprocessor systems are becoming more complex and facing increasing information processing requirements. To increase microprocessor system speed and throughput using parallel processing, manufacturers are designing microprocessor systems using multiple central processing unit (“CPU”) cores. Microprocessor systems may integrate multiple CPU cores a variety of ways. Commonly, each CPU core may be on a separate microprocessor die, and multiple microprocessor die are packaged together in one microprocessor system. Increasingly, more than one CPU core may be integrated on each microprocessor die.
Each microprocessor die requires auxiliary logic and circuits including system memory and/or cache memory. While some designs integrate CPU cores and memory on a single microprocessor die, some designs require more memory than is commonly placed on the same die as a CPU core. In these designs, a separate static random access memory (SRAM) die or dynamic random access memory (DRAM) die is packaged proximate to the microprocessor die.
To maximize system speed and density, system designers strive to place microprocessor die as physically proximal to one another and memory die as possible. However, increasing system density by placing microprocessor die in close physical proximity presents difficult technical challenges including providing adequate clean power to the microprocessor die and removing waste heat generated by the microprocessor and memory die.